This nonprovisional application claims priority under 35 U.S.C. xc2xa7119(a) on Patent Application No. P2001-21584 filed in Korea on Apr. 21, 2001, which is herein incorporated by reference.
1. Field of the Invention
This invention relates to a method of driving a liquid crystal display panel of dot inversion or line inversion system, and more particularly to a method of driving a liquid crystal display panel using sequentially applied superposed gate pulses.
2. Description of the Background Art
Generally, a liquid crystal display (LCD) controls a light transmittance of each liquid crystal cell in accordance with a video signal to display a picture. An active matrix LCD including a switching device for each liquid crystal cell is suitable for displaying a dynamic image. The active matrix LCD uses thin film transistors (TFTs) as switching devices.
The active matrix LCD can be made into a device that is smaller in size than the existing Braun tube. Therefore, the active matrix LCD has been widely used for a monitor for a personal computer, or a notebook computer as well as office automation equipment such as a copy machine, etc. and portable equipment such as a cellular phone and a pager, etc.
FIG. 1 shows a schematic configuration of a typical LCD.
Referring to FIG. 1, the LCD includes a gate driver 12 for driving gate lines GL1 to GLn on a liquid crystal display panel 10, and a data driver 14 for driving data lines DL1 to DLm crossing the gate lines GL1 to GLn. The LCD panel 10 has pixels PE which are each arranged at an area divided by the gate lines GL1 to GLn and the data lines DL1 to DLm. Each pixel includes a liquid crystal cell CLC for responding to an electric field to control a transmitted light amount, and a TFT for responding to gate signals at the gate lines GL1 to GLn to selectively connect the data lines DL1 to DLm to the liquid crystal cells CLC.
The gate driver 12 responds to a gate control signal from a timing controller 16 to drive n gate lines GL1 to GLn sequentially by one horizontal synchronous interval every frame. In response to a data control signal from the timing controller 16 the data driver 14 supplies pixel data to the data lines DL1 to DLn whenever the gate lines GL1 to GLn are enabled.
FIG. 2 shows a conventional equivalent circuit of each pixel PE on the LCD panel in FIG. 1.
Referring to FIG. 2, the pixel PE includes a TFT connected between the gate line GLn and the data line DL, and a liquid crystal cell ClC connected between a source terminal of the TFT and a common voltage line CL. During operation, the liquid crystal cell ClC charges a difference voltage between a video signal on the data line DL and a common voltage Vcom from the common voltage line CL during one horizontal synchronizing signal interval. The interval occurs when the TFT keeps a turn-on state, and that is when a gate high voltage is applied to the gate line GL. Thus, the difference voltage charged in the liquid crystal cell ClC becomes different depending on the polarity of a video signal and the data driver 14.
Such a LCD uses five driving methods such as a line inversion system, a column inversion system, a dot inversion system, a two-dot inversion system and a group inversion system so as to drive the liquid crystal cells of the liquid crystal display panel.
In the line inversion system, the polarities of data signals applied to the LCD panel become different depending on row lines, which correspond to the gate lines on the liquid crystal display panel, as shown in FIG. 3A. The polarities of the data signals are again inverted on a frame basis, as shown in FIG. 3B.
In the column inversion system, the polarities of data signals applied to the LCD panel become different depending on column lines, which correspond to the data lines on the liquid crystal display panel, as shown in FIG. 4A. Again, the polarities of the data signals may be inverted on a frame basis, as shown in FIG. 4B.
In the dot inversion system, as shown in FIG. 5A, contrary polarities of data signals are applied to adjacent liquid crystal cells for each column line and each row line on the liquid crystal display panel. As shown in FIG. 5B, the polarities of data signals applied to all liquid crystal cells of the LCD panel are inverted for every frame. In other words, when video signals of a certain frame are displayed, data signals are applied to the liquid crystal cells of the LCD panel such that positive polarity (+) and negative polarity (xe2x88x92) alternates as the liquid crystal cells go from the left upper side to the right side, and into the lower side, as shown in FIG. 5A. Subsequently, when video signals at the next frame are displayed, data signals applied to the liquid crystal cells are inverted to be contrary to the previous frame as shown in FIG. 5B.
In the dot inversion system, polarities of data signals are inverted at all pixels in the vertical and horizontal directions to have advantages of both the line inversion system and the column inversion system. As a result, a picture of excellent quality is provided. Further, the LCD panel driving methods adopting the dot inversion system has recently been widely utilized due to these advantages.
A panel with the TFT LCD tends toward a higher resolution and a larger scale picture. As the resolution of the LCD becomes higher, a high-speed operation is required to shorten the horizontal synchronizing signal interval. Thus, a width of a gate signal is not only reduced, but also the time permitting a video signal to be applied to the liquid crystal cell is reduced. This causes a disadvantage in that a time margin capable of charging a data voltage in a pixel in the case of a resolution of SXGA (1280*1024) or UXGA (1600*1200) is not sufficient.
To overcome this disadvantage, an attempt of pre-charging mutually superposing gate signals applied to any adjacent gate line has been made to allow input of data for the preceding pixel in advance prior to inputting real data.
This attempt is based on the assumptions that the first gate line to the nth gate line of the liquid crystal display panel should be GL1, GL2, GL3, . . . , GLi, . . . GLnxe2x88x921, GLn; the first data line to the mth data line be DL1, DL2, DL3, . . . , DLj, . . . , DLmxe2x88x921, DLm; a pixel supplied with a data at the jth data line DLj by a gate pulse at the ith gate line GLi is Pi,j; and a pixel supplied with a data at the jth data line DLj by a gate pulse at the (i+1)th gate line GLi+1 be Pi+1,j. 
In the prior art, video signals are applied in such a manner that signals at the two adjacent gate lines GLi and GLi+1 in correspondence with a pixel Pi,j and the next pixel Pi+1,j are superposed with each other. If a gate signal is applied to the ith gate line GLi, then video data is supplied to the pixel Pi,j. If signals of the two gate lines GLi and GLi+1 are superposed with each other, then a portion of a signal having a polarity different from the video signal that previously charged the pixel Pi+1,j is applied to change its polarity in advance with the aid of a video signal applied to the pixel Pi,j. This strategy is applicable to the column inversion system in which the pixels Pi,j and Pi+1,j have the same polarity at the same frame. However, such a driving method of merely superposing two adjacent gate signals can not be applied to the line inversion or dot inversion system in which a different polarity is applied to upper and lower adjacent pixels.
A pre-charging driving scheme applicable to the line inversion or dot inversion system has been disclosed in Japanese Patent Laid-open Gazette No. Pyung 6-118910. This scheme applies a sub-pulse in advance upon applying data to the preceding pixel having the same polarity prior to application of a main pulse of a gate signal.
However, such a scheme has the following problems. In the case of a higher resolution, the width of a main pulse of a gate signal applied to each gate line GL is reduced. The reduction causes difficulty in pulse-application driving of the LCD panel wherein a main pulse of a gate signal is applied to the nth gate line GLn, and simultaneously, a sub-pulse is applied to the (n+2)th gate line GLn+2; and after a main pulse is applied to the (n+1)th gate line GLn+1, a main pulse is applied to the (n+2)th gate line GLn+2 and, simultaneously, a sub-pulse is applied to the (n+2)th gate line. Furthermore, since the number of scanning lines of the panel is enlarged according to a higher resolution, the time margin large enough to completely charge a data voltage in the pixel is not sufficient due to a delay factor. This deficiency in the line margin causes a deterioration in a display quality such as a deterioration in a color or brightness expression.
Accordingly, it is an object of the present invention to provide a method of driving a liquid crystal display panel wherein an accurate data voltage is applied to a high-resolution and high-scale LCD panel to improve a charge rate of a pixel and a storage capacitor.
To achieve these and other objects, a method of driving a LCD panel according to one embodiment of the present invention includes the steps of sequentially applying first-polarity gate pulses to odd-numbered gate lines of the liquid crystal display panel such that a portion of the first-polarity gate pulses are superposed at at least adjacent odd-numbered gate lines of the odd-numbered gate lines; sequentially applying second-polarity gate pulses to even-numbered gate lines of the liquid crystal display panel such that a portion of the second-polarity gate pulses are superposed at least adjacent even-numbered gate lines of the even-numbered gate lines; and applying data pulses to data lines in synchronization with the gate pulses.
In the method, the even-numbered gate lines are turned off when the first polarity gate pulses are applied to the odd-numbered gate lines. On the other hand, the odd-numbered gate lines are turned off when the second polarity gate pulses are applied to the even-numbered gate lines.
In the method, a pulse width of the gate signal is larger than one horizontal scanning interval. Also, a pulse width of the superposing gate signal may be set to be less than 3 xcexcs.
Further, the data pulses applied to the adjacent data lines in the data lines for supplying the data pulses to the liquid crystal display panel have the polarities contrary to each other.